From 8edc6dc91f4a46cca81f99101fb13423615c586a Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Thu, 22 Aug 2019 11:30:52 +0530
Subject: arch/x86: Cache the TSEG region at the top of ram
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This patch adds new API for enabling caching for the TSEG region
and setting up required MTRR for next stage.

BUG=b:140008206
TEST=Build and boot CML-Hatch.

Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/arch/x86/include/arch/romstage.h |  9 +++++++++
 src/arch/x86/postcar_loader.c        | 18 ++++++++++++++++++
 2 files changed, 27 insertions(+)

(limited to 'src/arch')

diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h
index 2ac225875f..15c93f24bd 100644
--- a/src/arch/x86/include/arch/romstage.h
+++ b/src/arch/x86/include/arch/romstage.h
@@ -88,4 +88,13 @@ void run_postcar_phase(struct postcar_frame *pcf);
  */
 void late_car_teardown(void);
 
+/*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+void postcar_enable_tseg_cache(struct postcar_frame *pcf);
+
 #endif /* __ARCH_ROMSTAGE_H__ */
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index 10a9ca2ace..c6149ab26a 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -17,6 +17,7 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <rmodule.h>
 #include <romstage_handoff.h>
@@ -187,6 +188,23 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf)
 	stage_cache_add(STAGE_POSTCAR, prog);
 }
 
+/*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+void postcar_enable_tseg_cache(struct postcar_frame *pcf)
+{
+	uintptr_t smm_base;
+	size_t smm_size;
+
+	smm_region(&smm_base, &smm_size);
+	postcar_frame_add_mtrr(pcf, smm_base, smm_size,
+				MTRR_TYPE_WRBACK);
+}
+
 void run_postcar_phase(struct postcar_frame *pcf)
 {
 	struct prog prog =
-- 
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