From b6e97b19ae6a68556838c9801c7824302d72151f Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Sun, 9 Sep 2012 19:09:56 -0700 Subject: Add support for storing POST codes in CMOS This will use 3 bytes of CMOS to keep track of the POST code for the current boot while also leaving a record of the previous boot. The active bank is switched early in the bootblock. Test: 1) clear cmos 2) reboot 3) use "mosys nvram dump" to verify that the first byte contains 0x80 and the second byte contains 0xF8 4) powerd_suspend and then resume 5) use "mosys nvram dump" to verify that the first byte contains 0x81 and the second byte contains 0xFD Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151 Signed-off-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/1743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/console/post.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/console/post.c') diff --git a/src/console/post.c b/src/console/post.c index be2d0e9307..ab1afcf50a 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -21,6 +21,7 @@ #include #include +#include /* Write POST information */ @@ -38,6 +39,20 @@ void __attribute__((weak)) mainboard_post(uint8_t value) #define mainboard_post(x) #endif +#if CONFIG_CMOS_POST +static void cmos_post_code(u8 value) +{ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + cmos_write(value, CMOS_POST_BANK_0_OFFSET); + break; + case CMOS_POST_BANK_1_MAGIC: + cmos_write(value, CMOS_POST_BANK_1_OFFSET); + break; + } +} +#endif /* CONFIG_CMOS_POST */ + void post_code(uint8_t value) { #if !CONFIG_NO_POST @@ -45,6 +60,9 @@ void post_code(uint8_t value) print_emerg("POST: 0x"); print_emerg_hex8(value); print_emerg("\n"); +#endif +#if CONFIG_CMOS_POST + cmos_post_code(value); #endif outb(value, CONFIG_POST_PORT); #endif -- cgit v1.2.3