From d7b07af621627bbc40fb8481702b1fe7ab9b9c3c Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Thu, 9 Jan 2014 20:42:13 -0600 Subject: cpu/allwinner/a10: Clean up include order in Makefile.inc Alphabetize the sources for each stage (bootblock, rom, ram), and include twi.c in both romstage and ramstage. Change-Id: I5526f5a66f6600560005731a3ee536eb858f4ff0 Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/4639 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/cpu/allwinner/a10/Makefile.inc | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) (limited to 'src/cpu/allwinner/a10') diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 3e7b5355aa..03bc612457 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -1,23 +1,27 @@ +bootblock-y += bootblock_media.c bootblock-y += clock.c -bootblock-y += raminit.c bootblock-y += gpio.c bootblock-y += pinmux.c +bootblock-y += raminit.c bootblock-y += timer.c -bootblock-y += bootblock_media.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c +romstage-y += bootblock_media.c +romstage-y += clock.c +romstage-y += pinmux.c +romstage-y += timer.c +romstage-y += twi.c romstage-y += uart.c romstage-y += uart_console.c -romstage-y += bootblock_media.c -ramstage-y += uart.c -ramstage-y += uart_console.c +ramstage-y += bootblock_media.c +ramstage-y += clock.c +ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c -ramstage-y += monotonic_timer.c -ramstage-y += bootblock_media.c - +ramstage-y += uart.c +ramstage-y += uart_console.c real-target: $(obj)/BOOT0 -- cgit v1.2.3