From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Fri, 12 Oct 2018 10:54:30 +0200
Subject: cpu/amd: Use common AMD's MSR

Phase 1. Due to the size of the effort, this CL is broken into several
phases.

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
---
 src/cpu/amd/agesa/family15tn/model_15_init.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

(limited to 'src/cpu/amd/agesa/family15tn/model_15_init.c')

diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index fdcb9a2332..d188bcc84b 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -15,8 +15,10 @@
 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <string.h>
 #include <cpu/x86/pae.h>
@@ -24,8 +26,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
@@ -73,12 +73,12 @@ static void model_15_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(MCG_CAP);
+	msr = rdmsr(IA32_MCG_CAP);
 	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
 	for (i = 0; i < num_banks; i++)
-		wrmsr(MC0_STATUS + (i * 4), msr);
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
 	setup_lapic();
@@ -108,14 +108,14 @@ static void model_15_init(struct device *dev)
 		printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
 
 		/* Set SMM base address for this CPU */
-		msr = rdmsr(MSR_SMM_BASE);
+		msr = rdmsr(SMM_BASE_MSR);
 		msr.lo = SMM_BASE - (cpu_idx * 0x400);
-		wrmsr(MSR_SMM_BASE, msr);
+		wrmsr(SMM_BASE_MSR, msr);
 
 		/* Enable the SMM memory window */
-		msr = rdmsr(MSR_SMM_MASK);
+		msr = rdmsr(SMM_MASK_MSR);
 		msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
-		wrmsr(MSR_SMM_MASK, msr);
+		wrmsr(SMM_MASK_MSR, msr);
 	}
 
 	/* Write protect SMM space with SMMLOCK. */
-- 
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