From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 12 Oct 2018 10:54:30 +0200 Subject: cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/cpu/amd/agesa/family15tn/udelay.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/cpu/amd/agesa/family15tn/udelay.c') diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c index 3d40fc3b33..7ff4c5c7a8 100644 --- a/src/cpu/amd/agesa/family15tn/udelay.c +++ b/src/cpu/amd/agesa/family15tn/udelay.c @@ -21,6 +21,7 @@ */ #include +#include #include #include #include @@ -36,11 +37,11 @@ void udelay(uint32_t us) tsc_start = rdtscll(); /* Get the P-state. This determines which MSR to read */ - msr = rdmsr(0xc0010063); + msr = rdmsr(PS_STS_REG); pstate_idx = msr.lo & 0x07; /* Get FID and VID for current P-State */ - msr = rdmsr(0xc0010064 + pstate_idx); + msr = rdmsr(PSTATE_0_MSR + pstate_idx); /* Extract the FID and VID values */ fid = msr.lo & 0x3f; -- cgit v1.2.3