From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Fri, 12 Oct 2018 10:54:30 +0200
Subject: cpu/amd: Use common AMD's MSR

Phase 1. Due to the size of the effort, this CL is broken into several
phases.

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
---
 src/cpu/amd/family_10h-family_15h/model_10xxx_init.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

(limited to 'src/cpu/amd/family_10h-family_15h/model_10xxx_init.c')

diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index 50406744bb..2374503287 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -16,6 +16,8 @@
 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -28,11 +30,7 @@
 #include <cpu/amd/model_10xxx_rev.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/multicore.h>
-#include <cpu/amd/msr.h>
-
-#define MC0_STATUS 0x401
 
 static inline uint8_t is_gt_rev_d(void)
 {
@@ -110,12 +108,12 @@ static void model_10xxx_init(struct device *dev)
 	disable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(MCG_CAP);
+	msr = rdmsr(IA32_MCG_CAP);
 	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
 	for (i = 0; i < num_banks; i++)
-		wrmsr(MC0_STATUS + (i * 4), msr);
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 
 	enable_cache();
 
-- 
cgit v1.2.3