From c70eed1e6202c928803f3e7f79161cd247a62b23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 22 May 2018 02:18:00 +0300 Subject: device: Use pcidev_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król Reviewed-by: Arthur Heymans --- src/cpu/amd/family_10h-family_15h/model_10xxx_init.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/cpu/amd/family_10h-family_15h/model_10xxx_init.c') diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 4009ba19de..abf02a3690 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -142,7 +142,8 @@ static void model_10xxx_init(struct device *dev) uint32_t f5x80; uint8_t enabled; uint8_t compute_unit_count = 0; - f5x80 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 5)), 0x80); + f5x80 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 5), + 0x80); enabled = f5x80 & 0xf; if (enabled == 0x1) compute_unit_count = 1; @@ -161,11 +162,13 @@ static void model_10xxx_init(struct device *dev) uint32_t f0x160; uint8_t core_count = 0; uint8_t node_count = 0; - f0x60 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x60); + f0x60 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 0), + 0x60); core_count = (f0x60 >> 16) & 0x1f; node_count = ((f0x60 >> 4) & 0x7) + 1; if (is_gt_rev_d()) { - f0x160 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x160); + f0x160 = pci_read_config32( + pcidev_on_root(0x18 + id.nodeid, 0), 0x160); core_count |= ((f0x160 >> 16) & 0x7) << 5; } core_count++; -- cgit v1.2.3