From 03e6a455a38a5ba0b8146085c215fb324d161f36 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sun, 12 Feb 2017 10:31:15 -0700 Subject: amd/pi/hudson: Move APIC enable to CPU file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used. This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y. The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n. Original-Signed-off-by: Marshall Dawson Original-Reviewed-by: Marc Jones (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad) Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/18436 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/cpu/amd/pi/00670F00/fixme.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/cpu/amd/pi/00670F00/fixme.c') diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index 86f5acf58a..e7d7ba5878 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -88,4 +88,10 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); + } } -- cgit v1.2.3