From e33c50d74c518e0ebe1f2d8e88cebd023bb94bcf Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 6 Oct 2019 17:39:44 +0200 Subject: cpu/amd/{agesa,pi}: Select NO_FIXED_XIP_ROM_SIZE AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol. Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Paul Menzel --- src/cpu/amd/pi/00630F01/Kconfig | 4 ---- src/cpu/amd/pi/00660F01/Kconfig | 4 ---- src/cpu/amd/pi/00730F01/Kconfig | 4 ---- src/cpu/amd/pi/Kconfig | 12 +----------- 4 files changed, 1 insertion(+), 23 deletions(-) (limited to 'src/cpu/amd/pi') diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index e5e27b55b4..37025ab4bf 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -21,8 +21,4 @@ config CPU_ADDR_BITS int default 48 -config XIP_ROM_SIZE - hex - default 0x100000 - endif diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index 647044843a..374672da03 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -21,8 +21,4 @@ config CPU_ADDR_BITS int default 48 -config XIP_ROM_SIZE - hex - default 0x100000 - endif diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 43abc80aba..7ba49439eb 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -23,8 +23,4 @@ config CPU_ADDR_BITS int default 40 -config XIP_ROM_SIZE - hex - default 0x100000 - endif diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 973a086e9f..b33302ecef 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -28,23 +28,13 @@ config CPU_AMD_PI select SPI_FLASH if HAVE_ACPI_RESUME select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER select SMM_ASEG + select NO_FIXED_XIP_ROM_SIZE if CPU_AMD_PI config BINARYPI_LEGACY_WRAPPER def_bool n -config XIP_ROM_SIZE - hex - default 0x100000 - help - Overwride the default write through caching size as 1M Bytes. - On some AMD platforms, one socket supports 2 or more kinds of - processor family, compiling several CPU families agesa code - will increase the romstage size. - In order to execute romstage in place on the flash ROM, - more space is required to be set as write through caching. - config UDELAY_LAPIC_FIXED_FSB int default 200 -- cgit v1.2.3