From 8ae8c8822068ef1722c08073ffa4ecc25633cbee Mon Sep 17 00:00:00 2001
From: Marc Jones <marc.jones@amd.com>
Date: Wed, 19 Dec 2007 01:32:08 +0000
Subject: Initial AMD Barcelona support for rev Bx. These are the core files
 for HyperTransport, DDR2 Memory, and multi-core initialization.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 src/cpu/amd/quadcore/quadcore_id.c | 79 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 src/cpu/amd/quadcore/quadcore_id.c

(limited to 'src/cpu/amd/quadcore/quadcore_id.c')

diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
new file mode 100644
index 0000000000..e556d699ab
--- /dev/null
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <arch/cpu.h>
+#include <cpu/amd/quadcore.h>
+#ifdef __ROMCC__
+#include <cpu/amd/model_10xxx_msr.h>
+#endif
+
+//called by bus_cpu_scan too
+u32 read_nb_cfg_54(void)
+{
+	msr_t msr;
+	msr = rdmsr(NB_CFG_MSR);
+	return ( ( msr.hi >> (54-32)) & 1);
+}
+
+static inline u32 get_initial_apicid(void)
+{
+	return ((cpuid_ebx(1) >> 24) & 0xff);
+}
+
+//called by amd_siblings too
+#define CORE_ID_BIT 2
+#define NODE_ID_BIT 6
+struct node_core_id get_node_core_id(u32 nb_cfg_54)
+{
+	struct node_core_id id;
+	u32 core_id_bits;
+
+	u32 ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
+	if(ApicIdCoreIdSize) {
+		core_id_bits = ApicIdCoreIdSize;
+	} else {
+		core_id_bits = CORE_ID_BIT; //quad core
+	}
+
+	// get the apicid via cpuid(1) ebx[31:24]
+	if( nb_cfg_54) {
+		// when NB_CFG[54] is set, nodeid = ebx[31:26], coreid = ebx[25:24]
+		id.coreid = (cpuid_ebx(1) >> 24) & 0xff;
+		id.nodeid = (id.coreid>>core_id_bits);
+		id.coreid &= ((1<<core_id_bits)-1);
+	} else {
+		// when NB_CFG[54] is clear, nodeid = ebx[29:24], coreid = ebx[31:30]
+		id.nodeid = (cpuid_ebx(1) >> 24) & 0xff;
+		id.coreid = (id.nodeid>>NODE_ID_BIT);
+		id.nodeid &= ((1<<NODE_ID_BIT)-1);
+	}
+	return id;
+}
+
+static inline u32 get_core_num(void)
+{
+	return (cpuid_ecx(0x80000008) & 0xff);
+}
+
+static inline struct node_core_id get_node_core_id_x(void) {
+
+	return get_node_core_id( read_nb_cfg_54() );
+}
+
-- 
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