From 7635a60ca848b50ff4a0ac85a667adc7151a5abf Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Tue, 12 Feb 2013 00:07:38 +0800 Subject: armv7: Add emulation/qemu-armv7 board. To simplify testing ARM implementation, we need a QEMU configuration for ARM. The qemu-armv7 provides serial output, CBFS simulation, and full boot path (bootblock, romstage, ramstage) to verify the boot loader functionality. To run with QEMU: export QEMU_AUDIO_DRV=none qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom Verified to boot until ramstage loaded successfully by QEMU v1.0.50. Change-Id: I1f23ffaf408199811a0756236821c7e0f2a85004 Signed-off-by: Hung-Te Lin Reviewed-on: http://review.coreboot.org/2354 Reviewed-by: David Hendricks Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/cpu/armltd/Kconfig | 8 +++++++ src/cpu/armltd/Makefile.inc | 1 + src/cpu/armltd/cortex-a9/Kconfig | 5 ++++ src/cpu/armltd/cortex-a9/Makefile.inc | 2 ++ src/cpu/armltd/cortex-a9/bootblock.c | 17 ++++++++++++++ src/cpu/armltd/cortex-a9/cache.c | 44 +++++++++++++++++++++++++++++++++++ 6 files changed, 77 insertions(+) create mode 100644 src/cpu/armltd/Kconfig create mode 100644 src/cpu/armltd/Makefile.inc create mode 100644 src/cpu/armltd/cortex-a9/Kconfig create mode 100644 src/cpu/armltd/cortex-a9/Makefile.inc create mode 100644 src/cpu/armltd/cortex-a9/bootblock.c create mode 100644 src/cpu/armltd/cortex-a9/cache.c (limited to 'src/cpu/armltd') diff --git a/src/cpu/armltd/Kconfig b/src/cpu/armltd/Kconfig new file mode 100644 index 0000000000..b1f4c2ee4e --- /dev/null +++ b/src/cpu/armltd/Kconfig @@ -0,0 +1,8 @@ +config CPU_ARMLTD_CORTEX_A9 + depends on ARCH_ARMV7 + bool + default n + +if CPU_ARMLTD_CORTEX_A9 +source src/cpu/armltd/cortex-a9/Kconfig +endif diff --git a/src/cpu/armltd/Makefile.inc b/src/cpu/armltd/Makefile.inc new file mode 100644 index 0000000000..014742f056 --- /dev/null +++ b/src/cpu/armltd/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A9) += cortex-a9 diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig new file mode 100644 index 0000000000..7f35cfd653 --- /dev/null +++ b/src/cpu/armltd/cortex-a9/Kconfig @@ -0,0 +1,5 @@ +config BOOTBLOCK_CPU_INIT + string + default "cpu/armltd/cortex-a9/bootblock.c" + help + CPU/SoC-specific bootblock code. diff --git a/src/cpu/armltd/cortex-a9/Makefile.inc b/src/cpu/armltd/cortex-a9/Makefile.inc new file mode 100644 index 0000000000..d1e7edfdee --- /dev/null +++ b/src/cpu/armltd/cortex-a9/Makefile.inc @@ -0,0 +1,2 @@ +ramstage-y += cache.c +romstage-y += cache.c diff --git a/src/cpu/armltd/cortex-a9/bootblock.c b/src/cpu/armltd/cortex-a9/bootblock.c new file mode 100644 index 0000000000..8925439d2a --- /dev/null +++ b/src/cpu/armltd/cortex-a9/bootblock.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void bootblock_cpu_init(void); +void bootblock_cpu_init(void) +{ +} diff --git a/src/cpu/armltd/cortex-a9/cache.c b/src/cpu/armltd/cortex-a9/cache.c new file mode 100644 index 0000000000..957871dba7 --- /dev/null +++ b/src/cpu/armltd/cortex-a9/cache.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* + * Sets L2 cache related parameters before enabling data cache + */ +void v7_outer_cache_enable(void) +{ +} + +/* stubs so we don't need weak symbols in cache_v7.c */ +void v7_outer_cache_disable(void) +{ +} + +void v7_outer_cache_flush_all(void) +{ +} + +void v7_outer_cache_inval_all(void) +{ +} + +void v7_outer_cache_flush_range(u32 start, u32 end) +{ +} + +void v7_outer_cache_inval_range(u32 start, u32 end) +{ +} -- cgit v1.2.3