From 1d36d6df7dafea5a6f9dec80f4a3998470d440a2 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Thu, 30 Sep 2010 21:22:40 +0000 Subject: Use existing, readable MTRR #defines instead of hardcoding numbers. Replace $0x200 with $MTRRphysBase_MSR(0) etc. Also, move some #ifdef stuff a little bit around (should not affect any functionality) to make the Intel/AMD/VIA CAR implementations more similar and easier to compare. Signed-off-by: Uwe Hermann Acked-by: Myles Watson git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/intel/car/cache_as_ram.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/cpu/intel/car') diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 105f920b13..0cf5a2e669 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -196,11 +196,13 @@ clear_fixed_var_mtrr_out: wrmsr #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) + #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* enable write base caching so we can do execute in place * on the flash rom. */ -- cgit v1.2.3