From 97b30d86592af6bbf26f9c9bcaf95f13d5cab9ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 11 Feb 2019 11:39:47 +0200 Subject: cpu/intel/common: Add Nehalem for FSB detection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I194ac9eb6f03e7d3f5c96d6e6491e9ef32da9078 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/31339 Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/intel/common/fsb.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/cpu/intel/common') diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 92967859dd..83220de3bc 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -39,8 +39,11 @@ static int get_fsb(void) case 0x17: /* Enhanced Core */ ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; - case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ - case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ + case 0x25: /* Nehalem BCLK fixed at 133MHz */ + ret = 133; + break; + case 0x2a: /* SandyBridge BCLK fixed at 100MHz */ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ ret = 100; -- cgit v1.2.3