From 465eff61f4f0f730476aa7afe8819f1e6b118068 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Wed, 15 Jun 2016 06:07:55 +0300
Subject: Fix some cbmem.h includes
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Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15196
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/cpu/intel/haswell/cache_as_ram.inc | 1 -
 src/cpu/intel/haswell/romstage.c       | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

(limited to 'src/cpu/intel/haswell')

diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index ddbffbbc60..e09e74b6c2 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -17,7 +17,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <cbmem.h>
 
 /* The full cache-as-ram size includes the cache-as-ram portion from coreboot
  * and the space used by the reference code. These 2 values combined should
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 9932a508e5..9c08aa16ba 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/stages.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
-#include <cbfs.h>
+#include <cbmem.h>
 #include <romstage_handoff.h>
 #include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-- 
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