From fdf907e4405e5df84e9d5a29735e0506782d9c6d Mon Sep 17 00:00:00 2001 From: Tristan Corrick Date: Wed, 31 Oct 2018 02:27:12 +1300 Subject: cpu/intel/haswell: Only change the slow ramp rate for ULT CPUs On my system (Pentium G3258, ASRock H81M-HDS), changing the the slow ramp rate during `initialize_vr_config()` results in the following exception, causing the system to hang. CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting Code: 0 eflags: 00010006 cr2: 00000000 eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000 edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90 So, only change this setting for Haswell ULT CPUs, as suggested by the BIOS Writer's guide. Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90 Signed-off-by: Tristan Corrick Reviewed-on: https://review.coreboot.org/29384 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/haswell_init.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/cpu/intel/haswell') diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index c67ef1438d..2340dd0b03 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -333,9 +333,11 @@ static void initialize_vr_config(void) msr.hi &= ~(1 << (51 - 32)); /* Enable decay mode on C-state entry. */ msr.hi |= (1 << (52 - 32)); - /* Set the slow ramp rate to be fast ramp rate / 4 */ - msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); + if (haswell_is_ult()) { + /* Set the slow ramp rate to be fast ramp rate / 4 */ + msr.hi &= ~(0x3 << (53 - 32)); + msr.hi |= (0x01 << (53 - 32)); + } /* Set MIN_VID (31:24) to allow CPU to have full control. */ msr.lo &= ~0xff000000; wrmsr(MSR_VR_MISC_CONFIG, msr); -- cgit v1.2.3