From 0c781b2694b2c137d9761704954ea38be5ba8a15 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 1 Apr 2010 09:50:32 +0000 Subject: =?UTF-8?q?-=C3=82=C2=A0get=20rid=20of=20ASM=5FCONSOLE=5FLOGLEVEL?= =?UTF-8?q?=20except=20in=20two=20assembler=20files.=20-=20start=20naming?= =?UTF-8?q?=20all=20versions=20of=20post=20code=20output=20"post=5Fcode()"?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/intel/model_106cx/cache_as_ram.inc | 1 - 1 file changed, 1 deletion(-) (limited to 'src/cpu/intel/model_106cx/cache_as_ram.inc') diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 4781b0521c..da42d4dc66 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -20,7 +20,6 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#define post_code(x) intel_chip_post_macro(x) #include #include -- cgit v1.2.3