From 0a78f91fa378879ee0bd202aca3c839eed6c24be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 31 Jul 2012 23:47:09 +0300 Subject: Intel model_106cx: change CAR to HT-capable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are hyper-threading Atom CPUs, those would not enable L2 cache with model_6ex CAR code. Switch to code that can handle different number of threads and cores. Change-Id: I57328c231f8998f45f7b0d26c63b24585f8476dd Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/1384 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov Reviewed-by: James Laird Reviewed-by: Alexandru Gagniuc --- src/cpu/intel/model_106cx/Kconfig | 1 + src/cpu/intel/model_106cx/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'src/cpu/intel/model_106cx') diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 7a75ec1ba3..e26bf1fea5 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -3,6 +3,7 @@ config CPU_INTEL_MODEL_106CX select SMP select SSE2 select UDELAY_LAPIC + select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 018febc621..0b506b3807 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,4 +1,4 @@ driver-y += model_106cx_init.c subdirs-y += ../../x86/name -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc -- cgit v1.2.3