From 9265f89f4e892caa043f60272980e7cec81bce62 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 7 Jul 2019 23:58:34 +0300 Subject: arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber Reviewed-by: Furquan Shaikh Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) --- src/cpu/intel/model_2065x/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/intel/model_2065x') diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index f494e9b049..9a11b06e4d 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -13,11 +13,11 @@ subdirs-y += ../common ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += tsc_freq.c ramstage-y += acpi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c romstage-y += stage_cache.c ramstage-y += stage_cache.c -- cgit v1.2.3