From 4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 8 Jul 2013 16:23:54 -0600 Subject: cpu: Fix spelling Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/model_206ax/model_206ax_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/intel/model_206ax') diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index fa974e53cd..60288010da 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -39,7 +39,7 @@ #include "chip.h" /* - * List of suported C-states in this processor + * List of supported C-states in this processor * * Latencies are typical worst-case package exit time in uS * taken from the SandyBridge BIOS specification. @@ -374,7 +374,7 @@ static void configure_thermal_target(void) return; conf = lapic->chip_info; - /* Set TCC activaiton offset if supported */ + /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); -- cgit v1.2.3