From f6c20681d1d1fa66212ab58b6dc1e9112fe4651d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 2 Aug 2019 06:14:50 +0300 Subject: intel/nehalem,sandybridge: Move stage_cache support function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let garbage-collection take care of stage_cache_external_region() if it is no needed and move implementation to a suitable file already building for needed stages. Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE and (unused) aliasing of CONFIG_IED_REGION_SIZE as IED_SIZE. Change-Id: Idf00ba3180d8c3bc974dd3c5ca5f98a6c08bf34d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34672 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/intel/model_206ax/Makefile.inc | 4 ---- src/cpu/intel/model_206ax/model_206ax.h | 12 ++---------- src/cpu/intel/model_206ax/stage_cache.c | 28 ---------------------------- 3 files changed, 2 insertions(+), 42 deletions(-) delete mode 100644 src/cpu/intel/model_206ax/stage_cache.c (limited to 'src/cpu/intel/model_206ax') diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index f5de8c38fa..e723d74d78 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -24,10 +24,6 @@ smm-y += tsc_freq.c smm-y += finalize.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index c0d2434fe6..2dc929345d 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -81,17 +81,9 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -/* - * Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. - */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) - /* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) -# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" +#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) +# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c deleted file mode 100644 index 26dc5e03f9..0000000000 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "model_206ax.h" - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); -} -- cgit v1.2.3