From 1ac19e28eed4f6c53a4f295eb55500c65fc80f8d Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Wed, 27 Jul 2011 23:06:16 -0400 Subject: cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem fixed for model_6bx by r5945. Also change Deschutes CPU init sequence to match Katmai. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui Reviewed-on: http://review.coreboot.org/122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/model_65x/model_65x_init.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src/cpu/intel/model_65x/model_65x_init.c') diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 8f9fc66f45..ef9759782c 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -27,6 +27,7 @@ #include #include #include +#include static u32 microcode_updates[] = { #include "microcode-410-MU16522d.h" @@ -56,14 +57,17 @@ static u32 microcode_updates[] = { static void model_65x_init(device_t dev) { + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Initialize L2 cache */ + p6_configure_l2_cache(); + /* Turn on caching if we haven't already */ x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - /* Update the microcode */ - intel_update_microcode(microcode_updates); - /* Enable the local cpu apics */ setup_lapic(); }; -- cgit v1.2.3