From 784544b934d67dc85ccfcf33e04ff148045836ad Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 31 Oct 2011 17:07:52 +0100 Subject: Remove XIP_ROM_BASE The base is now calculated automatically, and all mentions of that config option were typical anyway (4GB - XIP_ROM_SIZE). Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/366 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/model_6ex/cache_as_ram.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/intel/model_6ex') diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 3a12cf6dd3..18ada2965b 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -98,7 +98,7 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx @@ -115,7 +115,7 @@ clear_mtrrs: movl $0x0000000f, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr -#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE */ /* Enable cache. */ movl %cr0, %eax -- cgit v1.2.3