From 1977b891c55a01e436b2aae1421f635b0c873778 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 12 Apr 2010 23:12:15 +0000 Subject: port latest model 6ex car changes to 6fx car, which is almost identical and currently unused. Just keep it in sync, we might need it some day. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/intel/model_6fx/cache_as_ram_disable.c | 88 -------------------------- 1 file changed, 88 deletions(-) delete mode 100644 src/cpu/intel/model_6fx/cache_as_ram_disable.c (limited to 'src/cpu/intel/model_6fx/cache_as_ram_disable.c') diff --git a/src/cpu/intel/model_6fx/cache_as_ram_disable.c b/src/cpu/intel/model_6fx/cache_as_ram_disable.c deleted file mode 100644 index e085efa170..0000000000 --- a/src/cpu/intel/model_6fx/cache_as_ram_disable.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - - - -void real_main(unsigned long bist); - -void stage1_main(unsigned long bist) -{ - unsigned int cpu_reset = 0; - - real_main(bist); - - /* No servicable parts below this line .. */ - -#ifdef CAR_DEBUG - /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ - unsigned v_esp; - __asm__ volatile ( - "movl %%esp, %0\n" - : "=a" (v_esp) - ); - printk(BIOS_SPEW, "v_esp=%08x\n", v_esp); -#endif - -cpu_reset_x: - - printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset); - printk(BIOS_SPEW, "No cache as ram now - "); - - /* store cpu_reset to ebx */ - __asm__ volatile ( - "movl %0, %%ebx\n\t" - ::"a" (cpu_reset) - ); - -#undef CLEAR_FIRST_1M_RAM -#include "cache_as_ram_post.c" - - /* For now: use rambase + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M of memory we - * preserve with the memcpy above. - */ - -#ifndef HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - - __asm__ volatile ( - "movl %0, %%ebp\n" - "movl %0, %%esp\n" - :: "a" (CONFIG_RAMBASE + HIGH_MEMORY_SAVE) - ); - - { - unsigned new_cpu_reset; - - /* get back cpu_reset from ebx */ - __asm__ volatile ( - "movl %%ebx, %0\n" - :"=a" (new_cpu_reset) - ); - - /* Copy and execute coreboot_ram */ - copy_and_run(new_cpu_reset); - } - - /* We will not return */ - printk(BIOS_DEBUG, "sorry. parachute did not open.\n"); -} -- cgit v1.2.3