From 53c1d204ed134017e9a04d68f175bb7f6c6e0915 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 15 Feb 2012 15:55:57 +0200 Subject: Intel cpus: use CPU_PHYSMASK_HI define in CAR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unifies models 6ex, 6fx and 106cx. Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/638 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/model_6fx/cache_as_ram.inc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/cpu/intel/model_6fx') diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index dfc4f3b2b9..25d8de28a1 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -22,6 +22,9 @@ #include #include +#define CPU_MAXPHYADDR 36 +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) + #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -71,7 +74,7 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable MTRR. */ @@ -119,7 +122,7 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -204,7 +207,7 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(0), %ecx movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx // 36bit address space + movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x39) -- cgit v1.2.3