From 9ed1456eff73d1a268eabb84176dd2a2107bf2d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 27 Jun 2012 16:14:49 +0300 Subject: Intel CPUs: execute microcode update only once per core MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Early HT-enabled CPUs do not serialize microcode updates within a core. Solve this by running microcode updates on the thread with the smallest lapic ID of a core only. Also set MTRRs once per core only. Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/1142 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle Reviewed-by: Stefan Reinauer --- src/cpu/intel/model_f2x/model_f2x_init.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'src/cpu/intel/model_f2x') diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index ec78672de6..8fd8abc7bf 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -48,11 +48,15 @@ static void model_f2x_init(device_t cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); - x86_setup_mtrrs(); - x86_mtrr_check(); - /* Update the microcode */ - intel_update_microcode(microcode_updates); + if (!intel_ht_sibling()) { + /* MTRRs are shared between threads */ + x86_setup_mtrrs(); + x86_mtrr_check(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + } /* Enable the local cpu apics */ setup_lapic(); -- cgit v1.2.3