From 1fa240a3c5d2a6e8cd63eff24f227abc3333753b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 12:05:38 +0100 Subject: cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Console is not yet enabled in bootblock. This will be done in a different CL. Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36774 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/cpu/intel/slot_1/Kconfig | 9 ++++++++- src/cpu/intel/slot_1/Makefile.inc | 3 ++- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'src/cpu/intel/slot_1') diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 00af79a440..791997499d 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -27,7 +27,6 @@ config SLOT_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE - select ROMCC_BOOTBLOCK config DCACHE_RAM_BASE hex @@ -37,4 +36,12 @@ config DCACHE_RAM_SIZE hex default 0x02000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x1000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x2000 + endif diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 599a5d0f24..0e4e7e6fd4 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -26,6 +26,7 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode -cpu_incs-y += $(src)/cpu/intel/car/p3/cache_as_ram.S +bootblock-y += ../car/p3/cache_as_ram.S +bootblock-y += ../car/bootblock.c postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c -- cgit v1.2.3