From f5c0d612966d1ab3e8c2f1d1ae1de9ae2438bbab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 14 Aug 2019 13:02:41 +0300 Subject: intel/smm: Provide common smm_relocation_params MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/smm/Makefile.inc | 1 + src/cpu/intel/smm/gen1/smmrelocate.c | 20 -------------------- src/cpu/intel/smm/smm_reloc.c | 16 ++++++++++++++++ 3 files changed, 17 insertions(+), 20 deletions(-) create mode 100644 src/cpu/intel/smm/Makefile.inc create mode 100644 src/cpu/intel/smm/smm_reloc.c (limited to 'src/cpu/intel/smm') diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc new file mode 100644 index 0000000000..a49b796caf --- /dev/null +++ b/src/cpu/intel/smm/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 5350d1c930..c177e9b952 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -39,17 +39,6 @@ #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; -}; - -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - /* On model_6fx, model_1067x and model_106cx SMRR functions slightly differently. The MSR are at different location from the rest and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */ @@ -88,15 +77,6 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params) wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; diff --git a/src/cpu/intel/smm/smm_reloc.c b/src/cpu/intel/smm/smm_reloc.c new file mode 100644 index 0000000000..860c095abf --- /dev/null +++ b/src/cpu/intel/smm/smm_reloc.c @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +struct smm_relocation_params smm_reloc_params; -- cgit v1.2.3