From bf10bc3e44ae0d85a9db189c7c84e380a1ec8aa7 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 1 Nov 2012 15:32:32 +0100 Subject: intel/socket_BGA956: enable speedstep, CAR, MMX, SSE All of these capabilities exist on all CPUs supported on this socket. Change-Id: I54f34e48e34bb6ab5b9954ab7ece8c2c3a1a8e67 Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/1664 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/socket_BGA956/Kconfig | 15 +++++++++++++++ src/cpu/intel/socket_BGA956/Makefile.inc | 1 + 2 files changed, 16 insertions(+) (limited to 'src/cpu/intel/socket_BGA956') diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index a764348e90..40f82aff88 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -1,3 +1,18 @@ config CPU_INTEL_SOCKET_BGA956 bool select CPU_INTEL_MODEL_1067X + select CACHE_AS_RAM + select MMX + select SSE + +if CPU_INTEL_SOCKET_BGA956 + +config DCACHE_RAM_BASE + hex + default 0xffaf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index a290e6997a..f93fa00e40 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -7,6 +7,7 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +subdirs-y += ../speedstep # Use Intel Core (not Core 2) code for CAR init, any CPU might be used. cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc -- cgit v1.2.3