From a27fba67a0dc8f2d2b991b08dbcd2eb485baa8d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 20 Jul 2016 08:50:38 +0300 Subject: intel model_106cx: Include CAR from socket directory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the socket layer is implemented with this CPU model, there could potentially be multiple CPU models included. There can be only one cache_as_ram include, so select it directly within the socket directory. Change-Id: Ia52bb152276eddfd1fb33ddb7f5d153ab8e8163c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15757 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/cpu/intel/socket_FCBGA559/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/cpu/intel/socket_FCBGA559') diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index e36c8b1b0c..082c47261b 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -6,3 +6,6 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading + +cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc +romstage-y += ../car/romstage.c -- cgit v1.2.3