From 7a8205ba353fdf7063791926f82f84c7a9491c35 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 3 Jun 2018 10:29:07 +0200 Subject: cpu/intel/car/core2: Prepare for POSTCAR_STAGE support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split of the model_6ex cache as ram to support POSTCAR_STAGE, which is also needed for future C_ENVIRONMENT_BOOTBLOCK. When using POSTCAR_STAGE the p4-netburst/exit_car.S is using since it is identical. Change-Id: Ibe9f065fdf1d702b73333ea7bb32daca15ba1293 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/26783 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/cpu/intel/socket_mPGA478MN/Makefile.inc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/cpu/intel/socket_mPGA478MN') diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc index 407861e164..ef89ac65a1 100644 --- a/src/cpu/intel/socket_mPGA478MN/Makefile.inc +++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc @@ -9,6 +9,11 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. +ifneq ($(CONFIG_POSTCAR_STAGE),y) cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +else +cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S +postcar-y += ../car/p4-netburst/exit_car.S +endif + romstage-y += ../car/romstage.c -- cgit v1.2.3