From ad874e3477ba391d8fe02b0cab6334be67e2e303 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 6 Sep 2012 17:46:30 +0200 Subject: Correct FSB reading in speedstep ACPI We parsed the MSR the wrong way, and didn't support some valid values. Change-Id: Ia42e3de05dd76b6830aaa310ec82031d36def3a0 Signed-off-by: Nico Huber Reviewed-on: http://review.coreboot.org/1656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/speedstep/acpi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/cpu/intel/speedstep/acpi.c') diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 249d9e47a8..d658c705ee 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -49,13 +49,15 @@ static int determine_total_number_of_cores(void) static int get_fsb(void) { - u32 fsbcode=(rdmsr(0xcd).lo >> 4) & 7; + const u32 fsbcode = rdmsr(0xcd).lo & 7; switch (fsbcode) { case 0: return 266; case 1: return 133; case 2: return 200; case 3: return 166; + case 4: return 333; case 5: return 100; + case 6: return 400; } printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n"); return 200; -- cgit v1.2.3