From 328d42f2d8e3b3eb9a451285a8d3e2f4c9fde029 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 8 Jul 2019 09:16:13 +0300 Subject: cpu/intel: Drop SMM_TSEG conditional MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SMM_TSEG is a qualifier between TSEG and ASEG memory region. ASEG is deprecated and not supported for these CPUs in coreboot codebase. Change-Id: I0602e04957a390473a2449e1c5ff951f9fdff73b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34133 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/model_1067x/Makefile.inc | 2 +- src/cpu/intel/model_106cx/Makefile.inc | 2 +- src/cpu/intel/model_6ex/Makefile.inc | 2 +- src/cpu/intel/model_6fx/Makefile.inc | 2 +- src/cpu/intel/model_f3x/Makefile.inc | 2 +- src/cpu/intel/model_f4x/Makefile.inc | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index caeab563a4..743e780a36 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -2,6 +2,6 @@ ramstage-y += model_1067x_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c subdirs-y += ../../x86/name subdirs-y += ../common -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index a1f2d0d1f0..6701e6fc18 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,7 +1,7 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name subdirs-y += ../common -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-1c-*) diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index cef2b0be86..e1491e6fb4 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,7 +1,7 @@ ramstage-y += model_6ex_init.c subdirs-y += ../../x86/name subdirs-y += ../common -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 ramstage-y += ../model_1067x/mp_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0e-*) diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index 9121e3b64a..f1d64b7454 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -2,6 +2,6 @@ ramstage-y += model_6fx_init.c subdirs-y += ../../x86/name subdirs-y += ../common ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index ed1eb5f7d8..1f2b564dac 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1,5 +1,5 @@ ramstage-y += model_f3x_init.c -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*) diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 196d63e462..7e853b07da 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1,5 +1,5 @@ ramstage-y += model_f4x_init.c -subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-04-*) -- cgit v1.2.3