From 40bcdba65219b28b3bf76bd97cb2906359554af3 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Fri, 20 Mar 2020 12:08:40 +0100
Subject: cpu/intel/common: Fix typo in comment

Change-Id: I9ff49adebc1156d33c648efb8e9854b13c0ef859
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/cpu/intel/common/common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/cpu/intel')

diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
index e38e068112..57a5fe602c 100644
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@@ -12,7 +12,7 @@ void set_feature_ctrl_lock(void);
 /*
  * Init CPPC block with MSRs for Intel Enhanced Speed Step Technology.
  * Version 2 is suggested--this function's implementation of version 3
- * may have room for improvment.
+ * may have room for improvement.
  */
 struct cppc_config;
 void cpu_init_cppc_config(struct cppc_config *config, u32 version);
-- 
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