From 66e0c4c8c46eec6063a7bb8933990cc5c203ec2e Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Wed, 4 Dec 2013 22:21:15 -0600 Subject: cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS CPU_MICROCODE_IN_CBFS was designed to mean that loading microcode updates from a CBFS file is supported, however, the name implies that microcode is present in CBFS. This has recently caused confusion both with contributions from Google, as well as SAGE. Rename this option to SUPPORT_CPU_UCODE_IN_CBFS in order to make it clearer that what is meant is "hey, the code we have for this CPU supports loading microcode updates from CBFS", and prevent further confusion. Change-Id: I394555f690b5ab4cac6fbd3ddbcb740ab1138339 Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/4482 Reviewed-by: Marc Jones Tested-by: build bot (Jenkins) --- src/cpu/intel/fsp_model_206ax/Kconfig | 6 +++--- src/cpu/intel/fsp_model_206ax/microcode_blob.c | 2 +- src/cpu/intel/haswell/Kconfig | 2 +- src/cpu/intel/microcode/microcode.c | 8 ++++---- src/cpu/intel/model_2065x/Kconfig | 2 +- src/cpu/intel/model_206ax/Kconfig | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index dbff6e01e0..6a008bf3b2 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -32,7 +32,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select CPU_MICROCODE_IN_CBFS if HAVE_FSP_BIN + select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select TSC_SYNC_MFENCE config BOOTBLOCK_CPU_INIT @@ -53,12 +53,12 @@ config ENABLE_VMX config CPU_MICROCODE_CBFS_LOC hex - depends on CPU_MICROCODE_IN_CBFS + depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xfff70000 config CPU_MICROCODE_CBFS_LEN hex - depends on CPU_MICROCODE_IN_CBFS + depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xC000 if CPU_INTEL_FSP_MODEL_306AX default 0x2800 if CPU_INTEL_FSP_MODEL_206AX diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c index 8bd790ade4..309ea75fa1 100644 --- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c +++ b/src/cpu/intel/fsp_model_206ax/microcode_blob.c @@ -18,7 +18,7 @@ */ unsigned microcode[] = { -#if IS_ENABLED(CONFIG_CPU_MICROCODE_IN_CBFS) +#if IS_ENABLED(SUPPORT_CPU_UCODE_IN_CBFS) #include "microcode_blob.h" #endif }; diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 7b6fc43257..03c3518b41 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -14,7 +14,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_MODULES select RELOCATABLE_MODULES select DYNAMIC_CBMEM - select CPU_MICROCODE_IN_CBFS + select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 1991ed8472..a68b24d180 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -30,11 +30,11 @@ #include #ifdef __PRE_RAM__ -#if CONFIG_CPU_MICROCODE_IN_CBFS +#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS #include #endif #else -#if CONFIG_CPU_MICROCODE_IN_CBFS +#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS #include #endif #include @@ -82,7 +82,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_CPU_MICROCODE_IN_CBFS +#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS #define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" @@ -192,7 +192,7 @@ void intel_update_microcode_from_cbfs(void) #endif } -#else /* !CONFIG_CPU_MICROCODE_IN_CBFS */ +#else /* !CONFIG_SUPPORT_CPU_UCODE_IN_CBFS */ void intel_update_microcode(const void *microcode_updates) { diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index b0f4e65031..9040ebcf0b 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select SMM_TSEG select HAVE_INIT_TIMER - select CPU_MICROCODE_IN_CBFS + select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 5b3f893943..426e613c9c 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select CPU_MICROCODE_IN_CBFS + select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE -- cgit v1.2.3