From 7129ccbd2330c42e9dc32c6e8127620556260c33 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Mon, 27 Feb 2017 01:01:55 +0100 Subject: cpu/intel/model_6{e,f}x: Unify init files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The init files for the Core Duo and Core 2 Duo are very similar. Reduce the differences, by using the same order for the include statements, the same blank lines, and the same comments. Change-Id: I0de060222a61a482377c760c6031d73c7e318edf Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/18506 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Martin Roth --- src/cpu/intel/model_6ex/model_6ex_init.c | 11 +++++++---- src/cpu/intel/model_6fx/model_6fx_init.c | 11 +++++------ 2 files changed, 12 insertions(+), 10 deletions(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index cc1260ea81..a93b113e0b 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -21,8 +21,8 @@ #include #include #include -#include #include +#include #include #include #include @@ -34,10 +34,10 @@ static void configure_c_states(void) msr_t msr; msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 15); // config lock until next reset. + msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo |= (1 << 3); //dynamic L2 + msr.lo |= (1 << 3); // dynamic L2 /* Number of supported C-States */ msr.lo &= ~7; @@ -50,7 +50,7 @@ static void configure_c_states(void) msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); wrmsr(MSR_PMG_IO_BASE_ADDR, msr); - /* set C_LVL controls */ + /* Set C_LVL controls and IO Capture Address */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); @@ -128,6 +128,9 @@ static void model_6ex_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); + /* Setup Page Attribute Tables (PAT) */ + // TODO set up PAT + /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index d29895b299..3a6319a62c 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -21,9 +21,9 @@ #include #include #include +#include #include #include -#include #include #include #include @@ -34,12 +34,11 @@ static void configure_c_states(void) msr_t msr; msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 14); // Deeper Sleep - msr.lo |= (1 << 10); // Enable IO MWAIT redirection - msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo |= (1 << 3); // Dynamic L2 + msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk + msr.lo |= (1 << 3); // dynamic L2 /* Number of supported C-States */ msr.lo &= ~7; @@ -47,7 +46,7 @@ static void configure_c_states(void) wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); - /* Set Processor MWAIT IO BASE */ + /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); wrmsr(MSR_PMG_IO_BASE_ADDR, msr); -- cgit v1.2.3