From 9d2762ca6f2c0414afdca210ba996db7a0956690 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 07:54:36 +0300 Subject: intel cache_as_ram: Fix typo in comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15223 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/cpu/intel/haswell/cache_as_ram.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index e09e74b6c2..2ccef786fa 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -236,7 +236,7 @@ before_romstage: post_code(0x38) - /* Setup stack as indicated by return value from ramstage_main(). */ + /* Setup stack as indicated by return value from romstage_main(). */ movl %ebx, %esp /* Get number of MTRRs. */ -- cgit v1.2.3