From dfeb04d46323b412e940ae5c4d52814b18670aa1 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sun, 12 Dec 2010 00:37:41 +0000 Subject: fix model 106cx Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/intel/model_106cx/model_106cx_init.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'src/cpu/intel') diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 2e38e775a6..1199315c48 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -97,14 +97,16 @@ static void configure_c_states(void) // TODO Do we want Deep C4 and Dynamic L2 shrinking? wrmsr(PMG_CST_CONFIG_CONTROL, msr); - // set P_BLK address - msr = rdmsr(PMG_IO_BASE_ADDR); - msr.lo = (PMB0 + 4) | (PMB1 << 16); + /* Set Processor MWAIT IO BASE (P_BLK) */ + msr.hi = 0; + // TODO Do we want PM1_BASE? Needs SMM? + //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); + msr.lo = ((PMB0_BASE + 4) & 0xffff); wrmsr(PMG_IO_BASE_ADDR, msr); - // set C_LVL controls - msr = rdmsr(PMG_IO_CAPTURE_ADDR); - msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted + /* set C_LVL controls */ + msr.hi = 0; + msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted wrmsr(PMG_IO_CAPTURE_ADDR, msr); } -- cgit v1.2.3