From 0867062412dd4bfe5a556e5f3fd85ba5b682d79b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 30 Jun 2009 15:17:49 +0000 Subject: This patch unifies the use of config options in v2 to all start with CONFIG_ It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/ppc/mpc74xx/Config.lb | 14 +++++++------- src/cpu/ppc/mpc74xx/mpc74xx.inc | 8 ++++---- 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'src/cpu/ppc/mpc74xx') diff --git a/src/cpu/ppc/mpc74xx/Config.lb b/src/cpu/ppc/mpc74xx/Config.lb index ee65e41f3b..86ce6faa44 100644 --- a/src/cpu/ppc/mpc74xx/Config.lb +++ b/src/cpu/ppc/mpc74xx/Config.lb @@ -1,19 +1,19 @@ ## ## CPU initialization ## -uses _RAMBASE -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_RAMBASE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE ## ## Use cache ram for initial setup ## -default USE_DCACHE_RAM=1 +default CONFIG_USE_DCACHE_RAM=1 ## Set dcache ram above coreboot image -default DCACHE_RAM_BASE=_RAMBASE+0x100000 +default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000 ## Dcache size is 32Kb -default DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc object cache.S diff --git a/src/cpu/ppc/mpc74xx/mpc74xx.inc b/src/cpu/ppc/mpc74xx/mpc74xx.inc index ba2c0018d5..0a3bfe8a09 100644 --- a/src/cpu/ppc/mpc74xx/mpc74xx.inc +++ b/src/cpu/ppc/mpc74xx/mpc74xx.inc @@ -30,7 +30,7 @@ * - enable L1 I/D caches, otherwise performance will be slow * - set up DBATs for the following regions: * - RAM (generally 0x00000000 -> 0x7fffffff) - * - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE) + * - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE) * - I/O (generally 0xfc000000 -> 0xfdffffff) * - the main purpose for setting up the DBATs is so the I/O region * can be marked cache inhibited/write through @@ -147,7 +147,7 @@ * IBATS * * IBAT0 covers RAM (0 -> 256Mb) - * IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE) + * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE) */ lis r2, 0@h ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER @@ -156,8 +156,8 @@ mtibatl 0, r2 isync - lis r2, _ROMBASE@h -#if ROM_SIZE > 1048576 + lis r2, CONFIG_ROMBASE@h +#if CONFIG_ROM_SIZE > 1048576 ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER #else ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER -- cgit v1.2.3