From c01d1380138e807fa941976d9f102fb1b200ad01 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Thu, 28 Mar 2013 19:04:58 -0700 Subject: exynos5250: Add function for configuring L2 cache This adds a new function to configure L2 cache for the exynos5250 and deprecates the old function. Change-Id: I9562f3301aa1e2911dae3856ab57bb6beec2e224 Signed-off-by: David Hendricks Reviewed-on: http://review.coreboot.org/2949 Reviewed-by: Ronald G. Minnich Reviewed-by: Gabe Black Tested-by: build bot (Jenkins) --- src/cpu/samsung/exynos5250/Makefile.inc | 3 -- src/cpu/samsung/exynos5250/cpu.c | 16 +++++++ src/cpu/samsung/exynos5250/cpu.h | 2 + src/cpu/samsung/exynos5250/exynos_cache.c | 80 ------------------------------- 4 files changed, 18 insertions(+), 83 deletions(-) delete mode 100644 src/cpu/samsung/exynos5250/exynos_cache.c (limited to 'src/cpu/samsung') diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 961b719505..74bc871f36 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,12 +9,10 @@ bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c -bootblock-y += exynos_cache.c romstage-y += clock.c romstage-y += clock_init.c romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. -romstage-y += exynos_cache.c romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c @@ -24,7 +22,6 @@ romstage-$(CONFIG_EARLY_CONSOLE) += uart.c #ramstage-y += tzpc_init.c ramstage-y += clock.c ramstage-y += clock_init.c -ramstage-y += exynos_cache.c ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index b6eae46a81..4bb06e8b4a 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,5 +1,7 @@ #include #include +#include +#include #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) @@ -33,3 +35,17 @@ struct chip_operations cpu_samsung_exynos5250_ops = { CHIP_NAME("CPU Samsung Exynos 5250") .enable_dev = enable_dev, }; + +void exynos5250_config_l2_cache(void) +{ + uint32_t val; + + /* + * Bit 9 - L2 tag RAM setup (1 cycle) + * Bits 8:6 - L2 tag RAM latency (3 cycles) + * Bit 5 - L2 data RAM setup (1 cycle) + * Bits 2:0 - L2 data RAM latency (3 cycles) + */ + val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); + write_l2ctlr(val); +} diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index 772e591cd5..a356e19990 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -118,4 +118,6 @@ /* helper function to map mmio address to peripheral id */ enum periph_id exynos5_get_periph_id(unsigned base_addr); +void exynos5250_config_l2_cache(void); + #endif /* _EXYNOS5250_CPU_H */ diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c deleted file mode 100644 index 2cb918d357..0000000000 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2012 Samsung Electronics. - * Arun Mankuzhi - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#include - -enum l2_cache_params { - CACHE_TAG_RAM_SETUP = (1<<9), - CACHE_DATA_RAM_SETUP = (1<<5), - CACHE_TAG_RAM_LATENCY = (2<<6), - CACHE_DATA_RAM_LATENCY = (2<<0) -}; - -/* - * Set L2 cache parameters - */ -static void exynos5_set_l2cache_params(void) -{ - unsigned int val = 0; - - asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); - - val |= CACHE_TAG_RAM_SETUP | - CACHE_DATA_RAM_SETUP | - CACHE_TAG_RAM_LATENCY | - CACHE_DATA_RAM_LATENCY; - - asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); -} - -/* - * Sets L2 cache related parameters before enabling data cache - */ -void v7_outer_cache_enable(void) -{ - exynos5_set_l2cache_params(); -} - -/* stubs so we don't need weak symbols in cache_v7.c */ -void v7_outer_cache_disable(void) -{ -} - -void v7_outer_cache_flush_all(void) -{ -} - -void v7_outer_cache_inval_all(void) -{ -} - -void v7_outer_cache_flush_range(u32 start, u32 end) -{ -} - -void v7_outer_cache_inval_range(u32 start, u32 end) -{ -} -- cgit v1.2.3