From 8cc846897132f6d6baa49118005815aefb5f560f Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 9 Feb 2013 15:56:04 +0100 Subject: Intel: Replace MSR 0xcd with MSR_FSB_FREQ And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/x86/lapic/apic_timer.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/cpu/x86/lapic') diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 53209fbbff..93e948fb0e 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -25,6 +25,7 @@ #include #include #include +#include /* NOTE: This code uses global variables, so it can not be used during * memory init. @@ -53,11 +54,11 @@ static int set_timer_fsb(void) switch (c.x86_model) { case 0xe: /* Core Solo/Duo */ case 0x1c: /* Atom */ - timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; + timer_fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ - timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; + timer_fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ -- cgit v1.2.3