From fcd5ace00b333ce31b11b02a2243dfbf39307f10 Mon Sep 17 00:00:00 2001 From: Eric Biederman Date: Thu, 14 Oct 2004 19:29:29 +0000 Subject: - Add new cvs code to cvs git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/x86/sse/Config.lb | 0 src/cpu/x86/sse/disable_sse.inc | 18 ++++++++++++++++++ src/cpu/x86/sse/enable_sse.inc | 14 ++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 src/cpu/x86/sse/Config.lb create mode 100644 src/cpu/x86/sse/disable_sse.inc create mode 100644 src/cpu/x86/sse/enable_sse.inc (limited to 'src/cpu/x86/sse') diff --git a/src/cpu/x86/sse/Config.lb b/src/cpu/x86/sse/Config.lb new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/cpu/x86/sse/disable_sse.inc b/src/cpu/x86/sse/disable_sse.inc new file mode 100644 index 0000000000..a18ea18643 --- /dev/null +++ b/src/cpu/x86/sse/disable_sse.inc @@ -0,0 +1,18 @@ + /* + * Put the processor back into a reset state + * with respect to the xmm registers. + */ + + xorps %xmm0, %xmm0 + xorps %xmm1, %xmm1 + xorps %xmm2, %xmm2 + xorps %xmm3, %xmm3 + xorps %xmm4, %xmm4 + xorps %xmm5, %xmm5 + xorps %xmm6, %xmm6 + xorps %xmm7, %xmm7 + + /* Disable sse instructions */ + movl %cr4, %eax + andl $~(3<<9), %eax + movl %eax, %cr4 diff --git a/src/cpu/x86/sse/enable_sse.inc b/src/cpu/x86/sse/enable_sse.inc new file mode 100644 index 0000000000..95724b71f7 --- /dev/null +++ b/src/cpu/x86/sse/enable_sse.inc @@ -0,0 +1,14 @@ + /* preserve BIST in %eax */ + movl %eax, %ebp + + /* + * Enable the use of the xmm registers + */ + + /* Enable sse instructions */ + movl %cr4, %eax + orl $(1<<9), %eax + movl %eax, %cr4 + + movl %ebp, %eax + -- cgit v1.2.3