From 036a581b8fa9478d4dba1bf9e576ee9cc0bead24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 20 Nov 2016 07:45:17 +0200 Subject: AGESA f14: Consolidate XIP cache MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do this like fam15tn to reduce code duplication. Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17563 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/amd/agesa/family14/fixme.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index d1bd0a1d78..ab10e3a704 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -92,6 +92,12 @@ void amd_initmmio(void) PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); } void amd_initenv(void) -- cgit v1.2.3