From 0377a369b9c34dd9e5e1002845e99d29dea55ca3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jan 2019 10:44:49 +0200 Subject: aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This board is the only user of these ancient chipsets, so we'll do all in one go. Also wipe out some extra headers. Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30688 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/intel/socket_mPGA604/Kconfig | 5 +++++ src/cpu/intel/socket_mPGA604/Makefile.inc | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index ab0cf8ab6e..ca2f7b36ee 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -10,6 +10,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select SSE select UDELAY_TSC select SIPI_VECTOR_IN_ROM + select C_ENVIRONMENT_BOOTBLOCK # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -26,4 +27,8 @@ config DCACHE_RAM_SIZE hex default 0x4000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + endif # CPU_INTEL_SOCKET_MPGA604 diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 371f7a6b6b..9e3b8d75bf 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -7,6 +7,8 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading -cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/bootblock.c + postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c -- cgit v1.2.3