From 092fe558ee20950faf29d8e7d581a2631e6e1bb4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 1 Nov 2019 07:13:09 +0200 Subject: intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Note that due to UNKNOWN_TSC_RATE, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the cpu. Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/36525 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/intel/slot_1/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 3d0522a09d..10001bdc5f 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -24,7 +24,8 @@ config SLOT_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6XX select NO_SMM - select NO_MONOTONIC_TIMER + select UDELAY_TSC + select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE config DCACHE_RAM_BASE -- cgit v1.2.3