From 0e1ea279d025887c6904b4bb559c7165b44c6dec Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 1 Sep 2017 19:23:35 +0300
Subject: AGESA vendorcode: Add ENABLE_MRC_CACHE option
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When selected, try to store and restore memory training
results from/to SPI flash. This change only pulls in
the required parts from vendorcode for the build.

Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/cpu/amd/agesa/Kconfig | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/cpu')

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 4605dd3ba9..602a9b0528 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -72,6 +72,14 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x10000
 
+config ENABLE_MRC_CACHE
+	bool "Use cached memory configuration"
+	default n
+	select SPI_FLASH
+	help
+	  Try to restore memory training results
+	  from non-volatile memory.
+
 config S3_DATA_POS
 	hex
 	default 0xFFFF0000
-- 
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