From 23f50166c64be0c1d3656ca67839843bf11a5274 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 3 Apr 2013 09:55:22 -0500 Subject: haswell: enable ROM caching If ROM caching is selected the haswell CPU initialization code will enable ROM caching after all other CPU threads are brought up. Change-Id: I75424bb75174bfeca001468c3272e6375e925122 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/3016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/haswell/haswell_init.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 0bb11a8ed0..18636b0840 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -551,6 +551,9 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); + + /* Enable ROM caching if option was selected. */ + x86_mtrr_enable_rom_caching(); } static struct device_operations cpu_dev_ops = { -- cgit v1.2.3