From 30b755be2b798c228745661393efd8f2fe42e6d8 Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Thu, 23 Jul 2015 22:31:51 +0530 Subject: Add SoC specific microcode update check in ramstage Some Intel SoCs which support SGX feature, report the microcode patch revision one less than the actual revision. This results in the same microcode patch getting loaded again. Add a SoC specific check to avoid reloading the same patch. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:286054 Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8 Signed-off-by: Patrick Georgi Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775 Original-Signed-off-by: Rizwan Qureshi Original-Reviewed-on: https://chromium-review.googlesource.com/287513 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11055 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/cpu/intel/microcode/microcode.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 3492bfd6c9..8791a2efc4 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,6 +28,7 @@ #include #include #include +#include #if !defined(__PRE_RAM__) #include @@ -95,6 +96,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch) if (current_rev == m->rev) return; +#if ENV_RAMSTAGE + /*SoC specific check to update microcode*/ + if (soc_skip_ucode_update(current_rev, m->rev)) { + printk(BIOS_DEBUG, "Skip microcode update\n"); + return; + } +#endif + msr.lo = (unsigned long)m + sizeof(struct microcode); msr.hi = 0; wrmsr(0x79, msr); @@ -202,3 +211,10 @@ void intel_update_microcode_from_cbfs(void) spin_unlock(µcode_lock); #endif } + +#if ENV_RAMSTAGE +__attribute__((weak)) int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id) +{ + return 0; +} +#endif -- cgit v1.2.3