From 3d5bb236aa6147ce24d9618f2d482e76eefc58c6 Mon Sep 17 00:00:00 2001
From: Patrick Georgi <patrick.georgi@coresystems.de>
Date: Sun, 9 May 2010 21:15:13 +0000
Subject: Move includes to where they are needed. This allows to simplify
 romstage.c files in mainboards.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 src/cpu/amd/car/post_cache_as_ram.c | 1 +
 src/cpu/amd/model_10xxx/defaults.h  | 2 ++
 src/cpu/amd/model_10xxx/init_cpus.c | 6 ++++++
 src/cpu/amd/quadcore/quadcore.c     | 1 +
 4 files changed, 10 insertions(+)

(limited to 'src/cpu')

diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 24ea8da5e6..58d38cd603 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -1,6 +1,7 @@
 /* 2005.6 by yhlu
  * 2006.3 yhlu add copy data from CAR to ram
  */
+#include <string.h>
 #include <arch/stages.h>
 #include "cpu/amd/car/disable_cache_as_ram.c"
 
diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 98918ec312..78c46d4eaf 100644
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <northbridge/amd/amdmct/amddefs.h>
+#include <cpu/amd/mtrr.h>
 
 /*
  * Default MSR and errata settings.
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 3a86be296f..a64cdd8874 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -18,6 +18,12 @@
  */
 
 #include "defaults.h"
+#include <stdlib.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mtrr.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+#include <northbridge/amd/amdht/AsPsDefs.h>
+#include <northbridge/amd/amdht/porting.h>
 
 //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
 #ifndef SET_FIDVID
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index d66f56c881..142a270125 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <console/console.h>
 
 #ifndef SET_NB_CFG_54
 	#define SET_NB_CFG_54 1
-- 
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