From 4c65bfc3e88fe6f4d6441fb7e51f78ed22dea709 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Tue, 10 Apr 2018 13:34:24 +0200
Subject: nb/intel/x4x: Use common code for SMM in TSEG

This also caches the TSEG region and therefore increases MTRR usage
a little in some cases.

Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.

Tested on Intel DG41WV, resume from S3 still works fine.

Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/x86/smm/smmrelocate.S | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'src/cpu')

diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 16bccbce45..bd12581a76 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -27,9 +27,6 @@
 #include <southbridge/intel/i82801dx/i82801dx.h>
 #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)
 #include <southbridge/intel/i82801ix/i82801ix.h>
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX)
-#include <southbridge/intel/i82801jx/i82801jx.h>
-
 #else
 #error "Southbridge needs SMM handler support."
 #endif
-- 
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