From 52b1e2814a2c31001df43190574cdc5f0ed4bcbb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 6 Jul 2019 07:57:20 +0300 Subject: intel/socket_mPGA604: Enable TSC_CONSTANT_RATE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can use intel/common implementation for tsc_freq_mhz(). Change-Id: I728732896ad61465fcf0f5b25a6bafd23bca235e Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34199 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/cpu/intel/model_f2x/Makefile.inc | 2 ++ src/cpu/intel/socket_mPGA604/Kconfig | 3 +++ 2 files changed, 5 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 9bb5dca626..5d60d21eda 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1,3 +1,5 @@ +subdirs-y += ../common + ramstage-y += model_f2x_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*) diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 1453f9962b..4ec46e0ac8 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,9 +9,12 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE select UDELAY_TSC + select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_TIMEBASE # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on -- cgit v1.2.3